The French patent application No. 83 16488 published under the number 2 553 541 in the name of INRIA describes an electronic circuit constituting a high-speed stable memory, and comprising: address, data input/output, and read and write instruction lines or interfaces suitable for being connected to an external processor; first and second independent non-volatile read/write memory assemblies having address inputs, read/write control inputs, and data inputs/outputs; and access control means connected firstly to the address interfaces and to the read/write control interfaces, and secondly to the address inputs and to the read/write control inputs of both memory assemblies in such a manner as to authorize access only to a designated portion in each of the two memory assemblies, on each occasion that a designated read or write operation is to take place, with said authorization being destroyed after said memory portion has been addressed.
Although this prior art high-speed stable memory has given satisfaction, in particular in a distributed computing system for running a public bidding or auction system, it nevertheless suffers from certain drawbacks.
One of these drawbacks lies in the fact that each elementary protected zone in the memory as seen from the processor remains closely bound to the hardware structure of the memory, i.e. to its component words and bits.
Another drawback, partially related to the first drawback, lies in that some of the verifications necessary for ensuring memory stability are performed by software, and are, in some respects, performed by the processor using said memory.
In addition, restarting after a non-rectifiable anomaly in the memory was left entirely under the control of the processor using the memory.
The present invention seeks to improve the prior art high-speed stable memory in order to remedy the above drawbacks.
It is specified as this point that the present invention is physically embodied in the form of a module or card having stable memory and including memory components per se together with other components. The entire assembly is referred to herein as "stable memory".
A first aim of the present invention is to ensure that the "atomicity" of the operations performed by the stable memory no longer relies to any great extent on the processor using the memory, and that this is true, in particular, for the mechanisms concerned with mutual exclusions, with copying, and with creating zones in the memory in the manner described below in greater detail.
The terms "atomicity" and "atomic" are used in this specification, as in the above-mentioned prior specification, to specify that once information has been presented for writing, it is certain that the information is either correctly written in full, or else that it is not written at all.
In particular, in the present invention steps are taken to ensure that two protected memory zones cannot overlap, which could happen if the processor using the memory were allowed to define the memory zones it uses on the basis of memory words which are themselves intrinsically protected by the stable memory.
Another aim of the invention is for the size of the protected memory zones to be independent from the hardware structure of the memory; an "object" is thus defined which is constituted by a subset of the words in the memory, regardless of whether said words are contiguous or not. An object may, in turn, be decomposed into sub-objects, which are groups of memory zones that need not necessarily be contiguous but which must necessary lie within the portion of the memory assigned to the object to which they belong.
Yet another aim of the present invention is to provide a stable memory of higher speed than before.